Synopsys jobs - Oregon
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| May 29 | Online Adjunct Faculty - School of Education, Special Education | American Public University System | Remote, OR |
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Reports to : Director of Faculty - School of Education Department: Academics School: Education Program: Teaching Location: Remote Date Posted : May 29, 2012 Date Closing: Open... more |
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| May 29 | Design Engineer - Microprocessor - Chip,... | Cybercoders | Portland, OR |
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- Chip, Timing, Synthesis, CPU, Synopsys, Perl, Logic, VHDL, RTL - Skills Required - Design Engineer, Hardware Engineer, Electrical Engineer, hardware engineer, timing engineer,... more |
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| May 29 | Online Adjunct Faculty - School of Education, Secondary Social Studies Educ | American Public University System | Remote, OR |
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Reports to : Director of Faculty - School of Education Department: Academics School: Education Program: Teaching Location: Remote Date Posted: May 29, 2012 Date Closing: Open... more |
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| May 25 | R&D Engineer, Sr Staff | Synopsys | Hillsboro, OR |
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Responsible for designing, developing, debugging, and maintaining core infrastructure components of a significant new static verification platform. The individual should be... more |
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| May 11 | Sr. Asic Design Engineer | Intel | Hillsboro, OR |
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based VLSI design methodology and relevant Synopsys EDA tools (DC, ICC, PrimeTime). - Demonstrate experience in scripting with Unix shell, Perl and/or Tcl. Preferred Skills: -... more |
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| May 11 | Staff ASIC Design Engineer | Intel | Hillsboro, OR |
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and full-chip Static Timing Analysis using Synopsys Primetime or equivalent commercial tool, timing constraints generation and management, and timing convergence. ? Expertise in... more |
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| May 08 | Analog Design Engineer - Bsee Verilog Rtl Synopsys Icc | Beaverton, OR | |
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* Synthesis and Timing analysis experience * Synopsys ICC, DFT tools, scripting in PERL and Shell PREFERRED: * Unix. Communication and team skills JOB DUTIES: * Work with the IP... more |
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| May 02 | Analog Design Engineer | CompuCom | Oregon |
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* Synthesis and Timing analysis experience * Synopsys ICC * DFT tools * Scripting in PERL and Shell * Communication and team skills required * Unix a plus Estimated Length of... more |
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| Apr 26 | Intern (Technical) | Synopsys | Hillsboro, OR |
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* Candidate must have 2+years of (educational) experience in the following areas: * Candidate must have 2+years of (educational) experience in the following areas: Interns/Temp more |
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| Apr 23 | Device Development Engineer | AMI Semiconductor | Gresham, OR |
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and wear out mechanisms. .TCAD experience: Synopsys platform preferred. .Layout and DRC experience: Mentor and/or Cadence platforms preferred. .Familiar with Linux and Unix... more |
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| Apr 20 | Device Development Engineer | On Semiconductor | Gresham, OR |
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and wear out mechanisms. TCAD experience: Synopsys platform preferred. Layout and DRC experience: Mentor and/or Cadence platforms preferred. Familiar with Linux and Unix Skilled... more |
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| Apr 19 | Regional Nurse Consultant | Executive Search Solutions | Portland, OR |
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Director of Risk Management Portland, OR We have a new employment opportunity in the Portland Metro / SW Washington area for a RN Risk Manager. This position will require travel... more |
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| Apr 19 | R&D Engineer, Sr Staff-Timing Analysis | Synopsys | Hillsboro, OR |
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team and with other product groups at Synopsys globally and across multiple time-zones. In addition, familiarity or experience with any of the following would be a plus: static... more |
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| Apr 16 | Analog Design Engineer | Beaverton, OR | |
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RTL skills * Experience with DFT technology, Synopsys or Mentor Graphics DFT tools, MBIST and ATPG tools, and scripting in PERL and Shell PREFERRED: * Experience with Unix *... more |
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| Apr 16 | Analog Engineer - 298761-PJF | Volt Information Sciences | Hillsboro, OR |
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Transfer Level, DFT/Design for Test Synopsys/Mentor Graphics DFT Tools, ... following: o Verilog RTL o DFT Technology o Synopsys or Mentor Graphics DFT Tools o MBIST... more |
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| Apr 13 | Analog Engineer | Volt Information Sciences | Hillsboro, OR |
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Transfer Level, DFT/Design for Test Synopsys/Mentor Graphics DFT Tools, ... following: * Verilog RTL * DFT Technology * Synopsys or Mentor Graphics DFT Tools * MBIST... more |
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| Apr 12 | Analog Custom Layout/Mask Design Engineer | Idhasoft | Hillsboro, OR |
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tandard cell Key Responsibilities: Floor planning Layout DRC/LVS verification and fix and implementation Hands-on experience with Cadence/Synopsys EDA tools for custom layout. more |
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| Apr 06 | Analog Layout/Mask Design | Hiregenics | Portland, OR |
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peed IO s or Standard cell Key Responsibilities Floor planning Layout DRC/LVS verification and fix and implementation Hands-on experience with Cadence/Synopsys EDA tools for... more |
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| Apr 04 | R&D Engineer, Sr I | Synopsys | Hillsboro, OR |
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Responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including operating systems, compilers, routers, networks,... more |
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| Mar 12 | Physical Design Engineer | Hiregenics | Portland, OR |
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Experience with Synopsys, Magma and/or cadence tools ... Magma Blast Fusion/Talus, Blast/Quartz Rail, Synopsys Primetime/Primetime-SI, Synopsys ICC... more |
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| Mar 08 | ASIC Design Engineer ( Synopsys) | Mavensoft Technologies | Hillsboro, OR |
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Years of Experience & Expertise Level: 4 yrs min SR LEVEL BS Project Description: -Laguna PCIe exerciser chip D step. Daily Responsibilities: -ASIC synthesis, layout edits, APR,... more |
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| Feb 28 | R&D Engineer, Sr II | Synopsys | Hillsboro, OR |
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as disseminating application expertise to Synopsys field support engineers to enable them to adapt mask synthesis solutions to customer-specific requirements. MS or PhD in... more |
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| Feb 13 | ASIC Design Engineer | Hirevelocity | Hillsboro, OR |
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based VLSI design methodology and relevant Synopsys EDA tools (DC, ICC, PrimeTime). - Demonstrate experience in scripting with Unix shell, Perl and/or Tcl. Preferred Skills: -... more |
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| Nov 11 | Design Engineer | Cybercoders | Portland, OR |
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- Chip, Timing, Synthesis, CPU, Synopsys, Perl, Logic, VHDL, RTL Design Engineer - Microprocessor - Chip, Timing, Synthesis, CPU If you are a Design Engineer with Microprocessor... more |
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| Nov 09 | Analog Layout Engineer | Idhasoft | Hillsboro, OR |
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d cells. Responsibilities will include floor planning, DRC/LVS verification and fix, and implementation Hands-on experience with Cadence /Synopsys EDA tools for custom layout. more |
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